Choice of the Optimum Timing Scheme for Rsfq Digital Circuits

Rapid Single Flux Quantum (RSFQ) logic is a superconducting digital circuit technology that has emerged as a possible alternative to advanced semiconductor technologies for large scale ultra-high speed, very low power digital applications. Timing of RSFQ circuits at frequencies of tens to hundreds of gigahertz is a challenging and still unresolved problem. In many circuit topologies of current medium to large scale RSFQ circuits synchronous clocking outperforms asynchronous schemes in speed, device/area overhead, and simplicity of the design procedure. Circuit yield and performance of large synchronous circuits is limited by process parameter variations. As a result, alternative synchronization techniques, including but not limited to asynchronous timing, should be considered for certain circuit topologies. We discuss our methodology for the optimal choice of the timing scheme for medium to large RSFQ circuits.